A number of digital counter designs are well-known in the art, including binary counters, one-hot counters, binary-coded decimal counters, and similar devices. Each of these counter designs finds application in different designs. For example, binary counters are very efficient, with an n-bit binary counter providing a capacity of 2n counts. Unfortunately, propagation delays produced by the carry operations required by binary counters hinder their overall performance, leaving them poorly suited for high speed applications. Conversely, one-hot counters provide excellent performance, but an n-bit counter can provide a capacity of only n counts. In many logic devices, such as field programmable gate arrays (FPGA) and complex programmable logic devices (CPLA), there is insufficient circuitry for the sheer number of components required to implement a one-hot counter of any significant count capacity. A Johnson counter architecture can cut the necessary number of components in half, but remains impractical for high speed, high capacity counters in programmable devices.